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general description the MAX11253 is a 6-channel, 16-bit delta-sigma adc that achieves exceptional performance while consuming very low power. sample rates up to 64ksps allow preci - sion dc measurements. the MAX11253 communicates via a spi serial interface and is available in a small (5mm x 5mm) tqfn package. the MAX11253 offers a 6.2nv/ hz noise programmable gain amplifier (pga) with gain settings from 1x to 128x. the integrated pga provides isolation of the signal inputs from the switched capacitor sampling network. the pga also enables the MAX11253 to interface directly with high-impedance sources without compromising available dynamic range. the MAX11253 operates from a single 2.7v to 3.6v analog supply, or split 1.8v analog supplies, allowing the analog input to be sampled below ground. the digital supply range is 1.7v to 2.0v or 2.0v to 3.6v, allowing communication with 1.8v, 2.5v, 3v, or 3.3v logic. applications analog i/o for programmable logic controllers weigh scales pressure sensors battery-powered instrumentation beneits and features high resolution for industrial applications that require a wide dynamic range ? 98db snr at 1000sps longer battery life for portable applications ? 2.2ma operating mode current ? 1a sleep current single or split analog supplies provide input voltage range flexibility ? 2.7v to 3.6v (single supply) or 1.8v (split supply) enables system integration ? low noise, 6.2nv/ hz pga with gains of 1, 2, 4, 8, 16, 32, 64, 128 ? 6-channel, fully differential input enables on-demand device and system gain and offset calibration ? user-programmable offset and gain registers robust performance in a small package ? -40 c to +125 c operating temperature range ? tqfn package, 5mm x 5mm 19-7650; rev 0; 6/15 ordering information appears at end of data sheet. MAX11253 c ref 1nf c0g ain5p ain5n gpo0 1nf c0g gpo1 ain0n ain0p 10nf refn refp 1f avdd 2.7v to 3.6v 2.0v to 3.6v gpognd capp capn 1nf c0g capreg 220nf 0603 x7r dgnd avss rdyb dout din sclk dvdd csb 1f resistive bridge measurement circuit, spi configuration rstb MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface typical application circuit evaluation kit available downloaded from: http:///
avdd to avss ..................................................... -0.3v to +3.9v avdd to dgnd .................................................... -0.3v to +3.9v dvdd to dgnd .................................................... -0.3v to +3.9v avss to dgnd .................................................. -1.95v to +0.3v dvdd to avss ..................................................... -0.3v to +3.9v avss to gpognd ............................................. -1.95v to +0.3v gpognd to dgnd ............................................ -1.95v to +0.3v ain_p, ain_n, refp, refn, capp, capn to avss ............................ -0.3v to the lower of +3.9v or (v avdd + 0.3v) gpo_ to gpognd .................................... -0.3v to the lower of +3.9v or (v avdd + 0.3v) capreg to avss ................................................ -0.3v to +3.9v capreg to dgnd ............................................... -0.3v to +2.1v all other pins to dgnd .............................. -0.3v to the lower of +3.9v or (v dvdd + 0.3v) maximum continuous current into any pins except gpognd pin ................................................... 50ma maximum continuous current into gpognd pin ............................................................. 100ma continuous power dissipation (t a = +70 c) tqfn (derate 34.5mw/ c above +70 c) ............... 2758.6mw operating temperature range ......................... -40c to +125 c junction temperature ...................................................... +150c storage temperature range ............................ -55c to +150 c soldering temperature (reflow) ....................................... +260c tqfn junction-to-ambient thermal resistance ( ja ).29c/w (note 1) (v avdd = 3.6v, v avss = 0v, v dvdd = 2.0v to 3.6v, v refp - v refn = v avdd , data rate = 1ksps, pga low-noise mode, single-cycle conversion mode (scycle = 1). t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.)(note 2) parameter symbol conditions min typ max units static performance (single-cycle conversion mode) noise voltage (referred to input) v n pga gain of 128, single-cycle mode at 1ksps data rate pga low- noise mode 0.31 v rms pga low- power mode 0.36 pga gain of 128, single-cycle mode at 12.8ksps data rate pga low- noise mode 0.87 pga low- power mode 1.19 pga gain of 128, continuous mode at 64ksps data rate pga low- noise mode 0.87 pga low- power mode 1.19 integral nonlinearity inl 3 15 ppm zero error z err after system zero-scale calibration 1 v zero drift z drift 50 nv/c full-scale error fse after system full-scale calibration (notes 3 and 4) 2 ppmfsr MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 2 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristicselectrical characteristics downloaded from: http:///
(v avdd = 3.6v, v avss = 0v, v dvdd = 2.0v to 3.6v, v refp - v refn = v avdd , data rate = 1ksps, pga low-noise mode, single-cycle conversion mode (scycle = 1). t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.)(note 2) parameter symbol conditions min typ max units full-scale error drift fse drift 0.05 ppmfsr/c common-mode rejection cmr dc rejection 110 130 db 50hz/60hz rejection (note 5) 110 130 dc rejection with pga gain 64 80 105 dc rejection with pga gain 128 95 avdd, avss supply rejection ratio psrra dc rejection 73 95 db 50hz/60hz rejection (note 5) 75 95 dc rejection with pga gain 128 65 75 dvdd supply rejection ratio psrrd dc rejection 105 115 db 50hz/60hz rejection (note 5) 105 115 dc rejection with pga gain 128 90 110 pgagain setting 1 128 v/v noise-spectral density nsd low-noise mode 6.2 nv/ hz low-power mode 10 gain error, not calibrated g err gain = 1 0.75 % gain = 2 1.2 gain = 4 2 gain = 8 3 gain = 16 4.5 gain = 32 6 gain = 64 5.5 gain = 128 2 output voltage range vout rng v avss + 0.3 v avdd - 0.3 v mux channel-to-channel isolation iso ch-ch dc 140 db general-purpose outputs resistance (on) r on gpo_ output current = 30ma, gpognd connected to avss 3.5 10 ? maximum current (on) i max per output 30 ma total from all outputs into gpognd pin (note 5) 90 ma MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 3 electrical characteristics (continued) downloaded from: http:///
(v avdd = 3.6v, v avss = 0v, v dvdd = 2.0v to 3.6v, v refp - v refn = v avdd , data rate = 1ksps, pga low-noise mode, single-cycle conversion mode (scycle = 1). t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.)(note 2) parameter symbol conditions min typ max units leakage current (off) i leak1 current into the gpognd pin with one individual gpo_ pin connected to 3v 0.4 na i leak3 current into the gpognd pin with all gpo_ pins connected to 3v 13 100 power-up delays (note 5) power-up time t pupslp sleep state (full power-down) to ldo wake-up v avdd = 2.7v, v dvdd = 2.0v, capreg = 220nf 23 45 s t pupsby standby state (analog blocks powered down, ldo on) to active 4 8 analog inputs/reference inputs common-mode input voltage range, v cm = (v ain_p + v ain_n )/2 cmi rng direct (pga bypassed) v avss v avdd v pga v avss + 0.4 v avdd - 1.3 input voltage range (ain_p, ain_n) v in(rng) direct (pga bypassed) v avss v avdd v pga v avss + 0.4 v avdd - 1.3 differential input voltage range (ain_p C ain_n) v in(diff) unipolar 0 v ref v bipolar -v ref +v ref dc input leakage i in_leak sleep state enabled 0.1 na differential input conductance g diff direct (pga bypassed) 11.6 a/v differential input current i diff pga enabled 1 na common-mode input conductance g cm direct (pga bypassed) 1 a/v common-mode input current i cm pga enabled 10 na reference differential input resistance r ref active state 26 k? reference differential input current i ref_pd standby and sleep state 1 na input capacitance c in direct (pga bypassed) 2.5 pf cp gain pga 0.25 ain_p, ain_n sampling rate f s 4.096 mhz reference voltage range (refp, refn) v ref(rng) (note 6) v avdd v MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 4 electrical characteristics (continued) downloaded from: http:///
(v avdd = 3.6v, v avss = 0v, v dvdd = 2.0v to 3.6v, v refp - v refn = v avdd , data rate = 1ksps, pga low-noise mode, single-cycle conversion mode (scycle = 1). t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.)(note 2) parameter symbol conditions min typ max units differential reference voltage range (refp C refn) v ref 1.5 v avdd v refp, refn sampling rate 4.096 mhz sensor fault detect currents current 1.1 a initial tolerance 10 % drift 0.3 %/c digital sinc filter response bandwidth (-3db) 0.203 x data rate hz settling time (latency) 5/ data rate s logic inputs input current idigi leak leakage current 1 a input low voltage v il 0.3 x v dvdd v input high voltage v ih 0.7 x v dvdd v input hysteresis v hys 200 mv gpio input low voltage v il_gpio 0.3 v gpio input high voltage v ih_gpio 1.2 v gpio input hysteresis v hys_gpio 20 mv logic outputs output low level v ol i ol = 1ma 0.4 v output high level (rdyb, dout, gpio_ ) v oh i oh = 1ma 0.9 x v dvdd v floating state leakage current idigo leak 10 a floating state output capacitance c digo 9 pf power requirements negative analog supply voltage v avss -1.8 0 v positive analog supply voltage v avdd v avss + 2.7 v avss + 3.6 v negative i/o supply voltage v dgnd 0 v MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 5 electrical characteristics (continued) downloaded from: http:///
(v avdd = 3.6v, v avss = 0v, v dvdd = 2.0v to 3.6v, v refp - v refn = v avdd , data rate = 1ksps, pga low-noise mode, single-cycle conversion mode (scycle = 1). t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.)(note 2) parameter symbol conditions min typ max units positive i/o supply voltage v dvdd capreg not driven by external supply 2.0 3.6 v dvdd and capreg pins connected together on the circuit board 1.7 2.0 capreg supply voltage v capreg internal ldo enabled 1.8 v when capreg pin is driven externally, ensure it is connected directly to dvdd pin 1.7 2.0 analog supply current i avdd(cnv) direct 2.2 3 ma pga low-power mode 3.5 4.7 pga low-noise mode 4.2 5.75 dvdd operating current i dvdd(cnv) v dvdd = 2.0v, ldo enabled 0.65 1.1 ma v dvdd = v capreg = 2.0v, ldo disabled 0.58 avdd sleep current i avdd(slp) v avdd = 3.6v, v avss = 0v, v dvdd = 2.0v 1 a dvdd sleep current i dvdd(slp) v dvdd = 2.0v 0.3 2.3 a avdd standby current i avdd(sby) v avdd = 3.6v, v avss = 0v, v dvdd = 2.0v 1.5 a dvdd standby current i dvdd(sby) v dvdd = 2.0v, ldo enabled 50 175 a v dvdd = v capreg = 2.0v, ldo disabled 2.5 uvlo threshold low to high v lh avdd, dvdd supply undervoltage lockout 0.8 1.2 1.65 v capreg supply undervoltage lockout 0.65 1.0 1.35 uvlo threshold high to low v hl avdd, dvdd supply undervoltage lockout 0.6 1.1 1.55 v capreg supply undervoltage lockout 0.45 0.95 1.3 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 6 electrical characteristics (continued) downloaded from: http:///
(v avdd = 3.6v, v avss = 0v, v dvdd = 2.0v to 3.6v, v refp - v refn = v avdd , data rate = 1ksps, pga low-noise mode, single-cycle conversion mode (scycle = 1). t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.)(note 2) electrical characteristics (continued) figure 1. spi timing diagram parameter symbol conditions min typ max units uvlo hysteresis v hys avdd, dvdd supply undervoltage lockout 4 % capreg supply undervoltage lockout 5 uvlo delay low to high or high to low t del avdd, dvdd supply undervoltage lockout 10 s capreg supply undervoltage lockout 3.5 uvlo glitch suppression t p avdd, dvdd supply undervoltage lockout 10 ns capreg supply undervoltage lockout 10 spi 16b data read sclk rdyb din csb dout msb 1 8 9 lsb high-z 16b data high-z t css0 t ds t doe t dh t dot t doh t dod t r1 t css1 t ch t cl t cp t csh1 t csw x 1 1 1 1 1 0 0 0 x 23 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 7 downloaded from: http:///
(v avdd = 3.6v, v avss = 0v, v dvdd = 1.7v to 3.6v, t a = t min to t max , unless otherwise noted. for output pins, c load = 20pf.) note 2: limits are 100% tested at t a = +25c, unless otherwise noted. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. note 3: full-scale error includes errors from gain and offset or zero-scale error. note 4: ppmfsr is parts per million of full-scale range. note 5: these specifications are guaranteed by design, characterization, or spi protocol. note 6: reference common mode (v refp + v refn )/2 (v avdd + v avss )/2 + 0.1v. parameter symbol conditions min typ max units sclk frequency f sclk note 5 applies to minimum value 0.05 8 mhz sclk clock period t cp 125 ns sclk pulse-width high t ch allow 40% duty cycle 50 ns sclk pulse-width low t cl allow 40% duty cycle 50 ns csb low setup t css0 csb low to 1st sclk rise setup 40 ns csb high setup t css1 csb rising edge to sclk rising edge setup time (note 5) 40 ns sclk fall hold t csh1 sclk falling edge to csb rising edge, sclk hold time 3 ns csb pulse width t csw minimum csb pulse-width high 40 ns din setup t ds din setup to sclk rising edge 40 ns din hold t dh din hold after sclk rising edge 0 ns dout transition t dot dout transition valid after sclk fall (note 5) 40 ns dout hold t doh output hold time remains valid after sclk fall (note 5) 3 ns dout disable t dod csb rise to dout disable (note 5) 25 ns csb fall to dout valid t doe (note 5) 0 40 ns sclk rise to rdyb 1 t r1 rdyb transitions from 0 to 1 on rising edge of sclk when lsb-1 of data is shifted onto dout (note 5) 0 40 ns rstb fall to rdyb 1 t r2 rdyb transition from 0 to 1 on falling edge of rstb, internal clock mode (note 5) 300 ns rdyb transition from 0 to 1 on falling edge of rstb, external clock mode, clock frequency = f clk (note 5) 2/f clk s MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 8 spi timing requirements downloaded from: http:///
(v avdd = +3.6v, v avss = 0v, v dvdd = +2.0v, v refp - v refn = v avdd ; t a = t min to t max , ldo enabled, pga enabled, unless oth - erwise noted. data rate = 1ksps, single-cycle conversion mode (scycle = 1) typical values are at t a = +25c.) -5 -4 -3 -2 -1 0 1 2 3 4 5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 inl (ppm) differential input (v) inl vs. input voltage t a = +25 c toc02 pga gain = 4v/v t a = - 40 c t a = +125 c 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.5 1 1.5 2 2.5 noise (v rms ) common - mode voltage (v) input - reffered noise vs. common - mode voltage toc3 t a = +25 c t a = - 40 c pga gain 128v/v t a = +125 c -5 -4 -3 -2 -1 0 1 2 3 4 5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 inl (ppm) differential input (v) inl vs. input voltage t a = +25 c toc01 bypass mode t a = - 40 c t a = +125 c -25 -20 -15 -10 -5 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 offset error ( lsb ) temperature ( c) offset error vs. temperature toc05 bypass mode pga = 4 -20 -15 -10 -5 0 5 2.7 3 3.3 3.6 offset error ( lsb ) v avdd (v) offset error vs. avdd voltage toc06 t a = +125 c t a = - 40 c t a = +25 c bypass mode -28 -23 -18 -13 -8 2.7 3 3.3 3.6 offset error ( lsb ) v avdd (v) offset error vs. avdd voltage toc07 t a = +125 c t a = - 40 c t a = +25 c pga = 4 -50 -40 -30 -20 -10 0 10 1.5 2.2 2.9 3.6 offset error ( lsb ) v refp - v refn (v) offset error vs. v refp - v refn toc08 bypass mode t a = +125 c t a = +25 c t a = - 40 c -55 -45 -35 -25 -15 -5 5 1.5 2.2 2.9 3.6 offset error ( lsb ) v refp - v refn (v) offset error vs. v refp - v refn toc09 pga = 4 t a = +25 c t a = +125 c t a = - 40 c 0 0.1 0.2 0.3 0.4 0.5 0.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 noise (v rms ) temperature ( oc ) input - reffered noise vs. temperature toc4 pga gain 128v/v MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 9 typical operating characteristics downloaded from: http:///
(v avdd = +3.6v, v avss = 0v, v dvdd = +2.0v, v refp - v refn = v avdd ; t a = t min to t max , ldo enabled, pga enabled, unless oth - erwise noted. data rate = 1ksps, single-cycle conversion mode (scycle = 1) typical values are at t a = +25c.) 8.0 8.1 8.1 8.2 8.2 8.3 8.3 8.4 8.4 8.5 8.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 frequency (mhz) temperature ( c) internal oscillator frequency vs. temperature toc10 8.16 8.17 8.17 8.18 8.18 8.19 8.19 8.20 8.20 1.7 1.8 1.9 2 frequency (mhz) v dvdd (v) internal oscillator frequency vs. dvdd voltage toc11 ldo disabled 8.16 8.17 8.17 8.18 8.18 8.19 8.19 8.20 8.20 2 2.5 3 3.5 frequency (mhz) v dvdd (v) internal oscillator frequency vs. dvdd voltage toc12 ldo enabled -130 -125 -120 -115 -110 -105 -100 10 100 1000 10000 100000 1000000 psrr (db) frequency on dvdd (hz) psrr vs. frequency on dvdd f sample = 64ksps bypass mode v dvdd = 2.1v 50mv p-p toc14 t a = -40 c t a = +25 c t a = +125 c -0.5 0.5 1.5 2.5 3.5 4.5 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 active current (ma) temperature ( c) active current vs. temperature toc15 pga low noise i dvdd i avdd -120 -115 -110 -105 -100 -95 -90 -85 10 100 1000 10000 100000 1000000 psrr (db) frequency on avdd (hz) psrr vs. frequency on avdd f sample = 64ksps bypass mode v avdd = 3.3v 50mv p-p toc13 t a = - 40 c t a = +25 c t a = +125 c 0 0.5 1 1.5 2 2.5 3 -40 -25 -10 5 20 35 50 65 80 95 110 125 sleep current (a) temperature ( c) sleep current vs. temperature toc16 i dvdd_sleep i avdd_sleep 3 3.5 4 4.5 5 5.5 6 2.7 3 3.3 3.6 active current (ma) v avdd (v) active current vs. avdd voltage toc18 pga low noise t a = +25 c t a = - 40 c t a = +125 c 1 10 100 -40 -25 -10 5 20 35 50 65 80 95 110 125 standby current (a) temperature ( c) i avdd_stby standby current vs. temperature toc17 i dvdd_stby MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface maxim integrated 10 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
(v avdd = +3.6v, v avss = 0v, v dvdd = +2.0v, v refp - v refn = v avdd ; t a = t min to t max , ldo enabled, pga enabled, unless oth - erwise noted. data rate = 1ksps, single-cycle conversion mode (scycle = 1) typical values are at t a = +25c.) 0.2 0.4 0.6 0.8 1 1.2 1.4 2 2.4 2.8 3.2 3.6 sleep current (a) v dvdd (v) sleep current vs. dvdd voltage toc22 ldo disabled t a = - 40 c t a = +25 c t a = +125 c 40 50 60 70 80 90 2 2.4 2.8 3.2 3.6 standby current (a) v dvdd (v) standby current vs. dvdd voltage toc23 ldo enabled t a = - 40 c t a = +25 c t a = +125 c -140 -120 -100 -80 -60 -40 -20 0 0 200 400 600 800 1000 thd (db) frequency (hz) thd vs. frequency toc25 bypass mode continuous f sample = 8ksps -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 amplitude (db) frequency (hz) output spectrum small - signal inputs bypass mode single cycle continous 100hz 3mv p-p sine input f sample = 4ksps toc24 90 95 100 105 110 115 120 -40 -25 -10 5 20 35 50 65 80 95 110 125 snr (db) temperature (oc) snr vs. temperature toc26 bypass mode continuous f sample = 1ksps 120hz sine input 0.3 0.8 1.3 1.8 2.3 2.8 2.7 3 3.3 3.6 standby current (a) v avdd (v) standby current vs. avdd voltage toc20 t a = - 40 c t a = + 125 c t a = +25 c 590 610 630 650 670 690 710 730 750 2 2.4 2.8 3.2 3.6 active current (a) v dvdd (v) active current vs. dvdd voltage toc21 ldo enabled t a = - 40 c t a = +25 c t a = +125 c MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface maxim integrated 11 www.maximintegrated.com typical operating characteristics (continued) downloaded from: http:///
pin name function 1 rdyb active-low data ready output. rdyb goes low when a new conversion result is available in the data register. when a read operation of a full output word completes, rdyb returns high . rdyb is always driven. 2 sclk spi serial clock input 3 avdd positive analog supply 4 avss negative analog supply 5 refp positive reference input 6 refn negative reference input 7 ain 0 n negative analog input 0 8 ain0p positive analog input 0 9 ain1n negative analog input 1 10 ain1p positive analog input 1 rdyb MAX11253 1 sclk 2 avdd 3 avss 4 refp 5 refn 6 ain0n 7 ain0p 8 ain1n 9 ain1p 10 ain2n 11 ain2p 12 ain3n 13 ain3p 14 ain4n 15 ain4p 16 gpo0 24 gpio0/clk 23 gpo1 22 gpognd 21 capp 20 capn 19 ain5p 18 ain5n 17 gpio1/sync 32 capreg 31 rstb 30 dvdd 29 dgnd 28 dout 27 csb 26 din 25 ep + MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 12 pin description pin coniguration downloaded from: http:///
pin name function 11 ain2n negative analog input 2 12 ain2p positive analog input 2 13 ain3n negative analog input 3 14 ain3p positive analog input 3 15 ain4n negative analog input 4 16 ain4p positive analog input 4 17 ain5n negative analog input 5 18 ain5p positive analog input 5 19 capn pga filter input. connect 1nf c0g capacitor between capp and capn. 20 capp pga filter input. connect 1nf c0g capacitor between capp and capn. 21 gpognd analog switch/general-purpose output, gnd terminal 22 gpo1 analog switch normally open terminal/general-purpose output 1. register controlled, close position connects gpo1 to gpognd. current sink only. 23 gpio0/ clk general-purpose i/o pin (default) or external clock signal for the device. when external clock mode is selected, provide a digital clock signal at this pin. the MAX11253 is speciied with a clock frequency of 8.192mhz. clock frequencies below 8.192mhz are supported. the data rate and digital ilter notch frequencies scale with the clock frequency. 24 gpo0 analog switch normally open terminal/general-purpose output 0. register controlled, close position connects gpo0 to gpognd. current sink only. 25 gpio1/ sync synchronization input (default) or general-purpose i/o pin. sync resets both the digital ilter and the modulator. connect sync from multiple MAX11253s in parallel to synchronize more than one adc to an external trigger . 26 capreg 1.8v subregulator output. connects to dvdd when driven externally by a 1.8v supply. connect a 220nf or larger capacitor between capreg and dgnd. 27 rstb active-low power-on-reset input 28 dvdd digital power supply, 1.7v to 3.6v 29 dgnd digital ground 30 dout serial data output 31 csb active-low chip-select input 32 din serial data input ep exposed pad. connect ep directly to avss plane. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 13 pin description (continued) downloaded from: http:///
detailed description the MAX11253 is a 16-bit delta-sigma adc that achieves exceptional performance consuming minimal power. sample rates up to 64ksps support precision dc mea - surements. the built-in sequencer supports scanning of selected analog channels, programmable conversion delay, and math operations to automate sensor monitor - ing. the fourth order delta-sigma modulator is unconditionally stable and measures six differential input voltages. the modulator is monitored for overrange conditions, which are reported in the status register. the digital filter is a variable decimation-rate sinc filter with overflow monitor - ing reported in the status register. the programmable gain differential amplifier (pga) is low noise and is programmable from 1 to 128. the pga buf - fers the modulator and provides a high-impedance input to the analog channels. system clock the MAX11253 incorporates a highly stable internal oscil - lator that provides the system clock. the system clock is trimmed to 8.192mhz, providing digital and analog timing. the MAX11253 also supports an external clock mode. voltage reference inputs the MAX11253 provides differential inputs refp and refn for an external reference voltage. connect the external reference directly across the refp and refn pins to obtain the differential reference voltage. the v refp voltage should always be greater than the v refn voltage, and the common-mode voltage range is between 0.75v and v avdd - 0.75v. analog inputs the MAX11253 measures six pairs of differential analog inputs (ain_p, ain_n) in direct connection or buffered through the pga. see the ctrl2: control register 2 (read/write) table for programming and enabling the pga or direct connect mode. the default coniguration is direct connect, with the pga powered down. bypass/direct connect the MAX11253 offers the option to bypass the pga and route the analog inputs directly to the modulator. this option lowers the power of the device since the pga is powered down. functional diagram timing clock generator delta-sigma adc digital filter serial interface 1.8v regulator mux pga ain0n ain0p ain1n ain1p ain2n ain2p ain3n ain3p ain4n ain4p ain5n ain5p avss avdd rdyb dout din sclk csb rstb gpognd capp capn refp refn 1a avdd 1a avss dgnd dvdd gpio0/clk gpio1/sync gpo0 gpo1 capreg MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 14 downloaded from: http:///
programmable gain ampliier (pga) the integrated pga provides gain settings from 1x to 128x. ( figure 2 ). direct connection is available to bypass the pga and directly connect to the modulator. the pgas absolute input voltage range is cmi rng and the pga output voltage range is vout rng , as specified in the electrical characteristics . note that linearity and performance degrade when the specified input common-mode voltage of the pga is exceeded. the input common-mode range and output common-mode range are shown in figure 3 . the fol - lowing equations describe the relationship between the analog inputs and pga output. ainp = positive input to the pga ainn = negative input to the pga capp = positive output of pga capn = negative output of pga v cm = input common mode gain = pga gain v ref = adc reference input voltage v in = v ainp - v ainn note: input voltage range is limited by the reference volt - age as described by v in v ref /gain ( ) ( ) ( ) ainp ainn cm capp cm ainp cm capn cm cm ainn vv v 2 v v gain v v v v gain v v ? ?? + = =+ = input voltage range the adc input range is programmable for bipolar (-v ref to +v ref ) or unipolar (0 to v ref ) ranges. the u/ b bit in the ctrl1 register conigures the MAX11253 for unipolar or bipolar transfer functions. data rates table 1 lists the available data rates for the MAX11253, rate[3:0] setting of the conversion command (see the modes and registers section). the single-cycle mode has an overhead of 48 digital master clocks that is approxi - mately 5.86s for a typical digital master clock frequency of 8.192mhz. the single-cycle effective column contains the data rate values including the 48 clock startup delays. the 48 clocks are required to stabilize the modulator at startup. in continuous conversion mode, the output data rate is five times the single-cycle rate up to a maximum of 64ksps. during continuous conversions, the output sample data requires five 24-bit cycles to settle to a valid conversion from an input step, pga gain changes, or a change of input channel through the multiplexer. if self-calibration is used, 48 additional master clocks are required to process the data per conversion. likewise, system calibration takes an additional 48 master clocks to complete. if both self and system calibration are used, it takes an additional 80 master clocks to complete. if self and/or system calibration are used, the effective data rate will be reduced by these additional clock cycles per conversion . noise performance the MAX11253 provides exceptional noise performance. snr is dependent on data rate, pga gain, and power mode. bandwidth is reduced at low data rates; both noise and snr are improved proportionally. tables 2 and 3 summarize the noise performance for both single-cycle and continuous operation versus data rate, pga gain, and power mode. figure 2. simplified equivalent diagram of the pga ainp r1 r1 r2 ainn capp capn c capp/n (c0g capacitor) a1a2 r3r3 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 15 downloaded from: http:///
table 1. available programmable data rates * the effective data rate is lower when the calibration is enabled due to additional mac (multiply/accumulate) operations required after the conversion is complete to perform the calibration adjustment. v avdd analog inputs pga output v avdd - 1.3v v avss + 0.4v v avss output voltage range = gain x input voltage range input voltage range common-mode input voltage v avdd - 0.3v v ref v avss + 0.3v figure 3. analog input voltage range compared to pga output range data rate (sps) rate[3:0] continuous single cycle conversion only conversion plus self- calibration* conversion plus self-calibration plus system calibration* 0000 1.9 50 50.01 49.99 49.98 0001 3.9 62.5 62.51 62.48 62.47 0010 7.8 100 99.98 99.92 99.88 0011 15.6 125 124.95 124.86 124.80 0100 31.2 200 199.80 199.57 199.41 0101 62.5 250 249.66 249.29 249.05 0110 125 400 398.98 398.05 397.44 0111 250 500 498.34 496.89 495.93 1000 500 800 796.11 792.41 789.97 1001 1000 1000 991.86 986.13 982.35 1010 2000 1600 1578.72 1564.26 1554.77 1011 4000 2000 1974.16 1951.60 1936.84 1100 8000 3200 3114.26 3058.48 3022.39 1101 16000 4000 3895.78 3808.89 3753.08 1110 32000 6400 6135.27 5922.49 5788.64 1111 64000 12800 11776.90 11017.10 10562.79 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 16 downloaded from: http:///
table 2. noise vs. pga mode and gain (single-cycle conversion) lp = low power, ln = low noise single-cycle conversion mode input-referred noise voltage ( v rms ) vs. pga gain setting data rate (sps) 1 2 4 8 16 32 64 128 lp ln lp ln lp ln lp ln lp ln lp ln lp ln lp ln 50 31.73 31.72 15.86 15.86 7.93 7.93 3.97 3.96 1.98 1.98 0.99 0.99 0.50 0.50 0.26 0.25 62.5 31.73 31.72 15.86 15.86 7.93 7.93 3.97 3.97 1.98 1.98 0.99 0.99 0.50 0.50 0.26 0.25 100 31.74 31.73 15.87 15.86 7.93 7.93 3.97 3.97 1.99 1.98 1.00 0.99 0.50 0.50 0.27 0.26 125 31.74 31.73 15.87 15.86 7.93 7.93 3.97 3.97 1.99 1.98 1.00 0.99 0.51 0.50 0.27 0.26 200 31.74 31.73 15.87 15.86 7.94 7.93 3.97 3.97 1.99 1.98 1.00 0.99 0.51 0.50 0.27 0.26 250 31.74 31.73 15.87 15.87 7.94 7.93 3.97 3.97 1.99 1.99 1.00 1.00 0.51 0.50 0.28 0.26 400 31.76 31.74 15.88 15.87 7.94 7.94 3.97 3.97 1.99 1.99 1.00 1.00 0.52 0.51 0.29 0.27 500 31.77 31.74 15.88 15.87 7.94 7.94 3.97 3.97 1.99 1.99 1.01 1.00 0.52 0.51 0.31 0.28 800 31.79 31.75 15.90 15.88 7.95 7.94 3.98 3.97 2.00 1.99 1.02 1.01 0.55 0.52 0.34 0.29 1,000 31.80 31.76 15.91 15.88 7.96 7.94 3.99 3.97 2.01 1.99 1.03 1.01 0.56 0.53 0.36 0.31 1,600 31.88 31.80 15.95 15.90 7.98 7.95 4.00 3.98 2.02 2.00 1.05 1.02 0.61 0.56 0.43 0.35 2,000 31.94 31.83 15.98 15.92 8.00 7.96 4.02 3.99 2.04 2.01 1.08 1.04 0.64 0.57 0.49 0.39 3,200 32.02 31.87 16.02 15.94 8.03 7.98 4.04 4.00 2.07 2.02 1.11 1.05 0.70 0.61 0.55 0.43 4,000 32.14 31.93 16.08 15.97 8.07 8.00 4.07 4.02 2.10 2.04 1.16 1.08 0.76 0.64 0.64 0.49 6,400 32.55 32.14 16.31 16.09 8.20 8.07 4.17 4.07 2.21 2.10 1.31 1.16 0.95 0.76 0.87 0.64 12,800 33.52 32.65 16.81 16.35 8.48 8.22 4.37 4.18 2.41 2.21 1.58 1.33 1.27 0.97 1.19 0.87 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 17 downloaded from: http:///
serial interface the MAX11253 interface is fully compatible with spi, qspi?, and microwire?-standard serial interfaces. the spi interface provides access to on-chip registers that are 8 bits to 24 bits wide. the interface consists of the standard spi signals csb, sclk, din, and dout. an additional rdyb output signals data availability. csb (chip select) csb is an active-low chip-select input to communicate with the MAX11253. csb transitioning from low to high is used to reset the spi interface. when csb is low, data is clocked into the device from din on the rising edge of sclk. data is clocked out of dout on the falling edge of sclk. when csb is high, sclk and din are ignored and dout is high impedance, allowing dout to be shared with other devices. sclk (serial clock) the sclk is used to synchronize data communication between the host device and the MAX11253. data is shifted in on the rising edge of sclk and data is shifted out on the falling edge of sclk. sclk remains low when not active. din (serial data input)data present on din is clocked into internal registers on the rising edge of sclk. dout (serial data output) the dout pin is actively driven when csb is low and high impedance when csb is high. data is shifted out on dout on the falling edge of sclk. rdyb (data ready) rdyb indicates the adc conversion status and the avail - ability of the conversion result. when rdyb is low, a conversion result is available. when rdyb is high, a con - version is in progress and the data for the current conver - sion is not available. rdyb is driven high after a complete read of the data register. rdyb resets to high four master clock cycles prior to the next data register update. if data was read, then rdyb transitions from high to low at the output data rate. if the previous data was not read, then the rdyb transitions from low to high for four master clock cycles and then transitions from high to low. in continuous mode, rdyb remains high for the first four conversion results and on the 5th result, rdyb goes low. table 3. noise vs. pga mode and gain (continuous conversion) lp = low power, ln = low noise qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor corporation. continuous conversion mode input-referred noise voltage ( v rms ) vs. pga gain setting data rate (sps) 1 2 4 8 16 32 64 128 lp ln lp ln lp ln lp ln lp ln lp ln lp ln lp ln 15.6 31.72 31.72 15.86 15.86 7.93 7.93 3.96 3.96 1.98 1.98 0.99 0.99 0.50 0.50 0.25 0.25 31.2 31.72 31.72 15.86 15.86 7.93 7.93 3.97 3.96 1.98 1.98 0.99 0.99 0.50 0.50 0.25 0.25 62.5 31.72 31.72 15.86 15.86 7.93 7.93 3.97 3.96 1.98 1.98 0.99 0.99 0.50 0.50 0.25 0.25 125 31.73 31.72 15.86 15.86 7.93 7.93 3.97 3.97 1.98 1.98 0.99 0.99 0.50 0.50 0.26 0.25 250 31.74 31.73 15.87 15.86 7.93 7.93 3.97 3.97 1.99 1.98 1.00 0.99 0.51 0.50 0.27 0.26 500 31.75 31.73 15.88 15.87 7.94 7.93 3.97 3.97 1.99 1.99 1.00 1.00 0.52 0.51 0.29 0.27 1000 31.78 31.75 15.89 15.87 7.95 7.94 3.98 3.97 2.00 1.99 1.02 1.00 0.54 0.52 0.33 0.29 2000 31.83 31.77 15.92 15.89 7.97 7.95 3.99 3.98 2.01 2.00 1.04 1.02 0.58 0.54 0.39 0.32 4000 31.93 31.82 15.97 15.91 8.00 7.96 4.02 3.99 2.04 2.01 1.08 1.04 0.64 0.57 0.48 0.38 8000 32.04 31.88 16.03 15.95 8.03 7.98 4.05 4.01 2.07 2.03 1.12 1.06 0.72 0.62 0.58 0.45 16000 32.14 31.93 16.08 15.97 8.07 8.00 4.07 4.02 2.10 2.04 1.16 1.08 0.76 0.64 0.65 0.50 32000 32.61 32.19 16.35 16.11 8.23 8.08 4.18 4.08 2.22 2.11 1.31 1.16 0.99 0.79 0.89 0.66 64000 34.51 33.19 16.99 16.45 8.57 8.26 4.41 4.20 2.42 2.21 1.56 1.31 1.32 1.00 1.19 0.87 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 18 downloaded from: http:///
for sequencer mode 2 and sequencer mode 3, the rdyb behavior for a multichannel conversion can be controlled by the seq:rdyben bit. the default value of seq:rdyben is 0. when set to 0, rdyb behaves the same for multichannel conversion and single chan - nel operation. the rdyb toggles high to low after each channel is ready to update its corresponding data register. after the channel data is read, the rdyb will reset back to 1. if the channel data is not read and the next chan - nel is ready to update its data, the rdyb will toggle low to high four cycles before the data update (similar to a single channel operation), and then toggle high to low indicating the new channels conversion data is available. if n channels are enabled, rdyb will toggle high to low n times. if seq:rdyben is set to 1, the rdyb event for each channel is suppressed. the rdyb toggles high to low when the last channel is ready to update its corre - sponding data register and a single high to low transition happens. the stat:srdy[5:0] bits get set to 1 when their corre - sponding channel finishes converting, irrespective of the rdyben setting for sequencer modes 2 and 3. the con - version status is available by reading the stat:mstat bit. this stays high as long as the modulator is converting. see figure 4 for timing of rdyb. spi incomplete write command termination in case of register writes, the register values get updated every 8th clock cycle with a byte of data starting from the msb. a minimum of 16 sclks are needed to write the first byte of data in a multibyte register or for an 8-bit register. for example, a 24-bit register write requires 8 sclks for register access byte and 24 sclks (data bits to be written). if only 15 sclks were issued out of the 32 expected, the register value will not be updated. at least 16 sclks are required to update the msb byte. for example, when the user issues a write command for a 24-bit register write and terminates after 16 sclks, only the msb byte, bits 23 to 16 of the register are updated. bits 15 to 0 retain the old value of the register. spi incomplete read command termination the spi interface stays in read mode for as long as csb stays low independent of the number of sclks issued. the csb pin must be toggled high to remove the device from the bus and reset the internal spi controller. any activity on the din pin is ignored while in the register read mode. the read operation is terminated if the csb pin is toggled high before the maximum number of sclks is issued. when reading from data registers, the behavior of rdyb will depend on how many bits are read. if at least 23 bits are read, the read operation is complete and rdyb resets to high. if the user reads less than 23 bits, internally the logic considers the read incomplete, and rdyb stays low. the user can initiate a new read within the same conver - sion cycle; however, the new 24-bit read must complete before the next data register update. spi timing characteristics the spi timing diagrams illustrating command byte and register access operations are shown in figure 5 to figure 8. the MAX11253 timing allows for the input data to be changed by the user at both rising and falling edges of sclk. the data read out by the device on sclk falling edges can be sampled by the user on subsequent rising or falling edges. figure 4. timing of rdyb in all conversion configurations: single-cycle, single-cycle continuous, and continuous. in sequencer mode 1 and in sequencer modes 2 and 3, with seq:rdyben=0 n = 1. in sequencer modes 2 and 3 with seq:rdyben=1 n = number of active channels. csb/sclk/din rdyb scycle=1', contsc=1' rdyb n t cnv scycle=1',contsc=0' rdyb t cnv 5 t cnv scycle=0',contsc=x' data not retrieved dataretrieved convert commands t cnv n t cnv MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 19 downloaded from: http:///
figure 6. spi register write timing diagram figure 5. spi command byte timing diagram sclk rdyb din csb dout 1 8 high-z high-z t css0 t ds t doe t dh t dod t css1 t ch t cl t cp t csh1 x 1 1 rs2 rs4 rs3 t csw x spi 8b register write rs1 rs0 x 16 d7 0 d6 d5 d4 d3 d2 d1 d0 x sclk rdyb din csb dout 1 8 high-z high-z t css0 t ds t doe t dh t dod t css1 t ch t cl t cp t csh1 x 1 0 mode 0 mode 1 t csw x spi command write byte rate 2 rate 1 rate 0 x rate 3 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 20 downloaded from: http:///
figure 7. spi register read timing diagram. for read patterns, the user may latch the MAX11253 output data on either rising edges (9C16) running at minimum latency or falling edges 9C16 running at increased latency. figure 8. spi data readout timing diagram sclk rdyb din csb dout 1 8 high-z high-z t css0 t ds t doe t dh t dod t css1 t ch t cl t cp t csh1 x 1 1 rs2 rs4 rs3 t csw x spi 8b register read rs1 rs0 x 16 1 x d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x t dot t doh 8b data spi 24b data read sclk rdyb din csb dout msb 1 8 9 lsb high-z 24b data high-z t css0 t ds t doe t dh t dot t doh t dod t r1 t css1 t ch t cl t cp t csh1 t csw x 1 1 1 1 1 0 0 0 x 31 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 21 downloaded from: http:///
modes and registers the MAX11253 interface operates in two fundamental modes, either to issue a conversion command or to access registers. the mode of operation is selected by a command byte. every spi transaction to the MAX11253 starts with a command byte. the command byte begins with the msb (b7) set to 1. the next bit (b6) determines whether a conversion command is sent or register read/ write access is requested. during a register read/write access, hold csb low for the entire read or write operation and pull csb high at the end of the command. for example, if the command is to read a 16-bit data register, hold csb low for 24 sclk cycles (8 cycles for the command byte plus 16 cycles for the data). csb transitions must not occur near the rising edge of sclk and must conform to the setup and hold timing detailed in the timing section. see spi timing requirements table. command byte the conversion command sets the mode of operation (conversion, calibration, or power-down) as well as the conversion speed of the MAX11253. the register read/ write command specifies the register address as well as the direction of the access (read or write). channel sequencingchanging sequencer modes mode exit (see table 8 . register map for register definitions) to exit any of the three sequencer modes at any time program the following sequence: 1) issue a power-down command to exit the conver - sion process to standby or sleep, as defined in ctrl1:pd[1:0]: a. write a conversion command byte (see table 4 . command byte definition) and set mode[1:0] of the command byte to 01 2) wait for stat:pdstat[1:0] = 01 ( sleep ) or stat:pdstat[1:0] = 10 ( standby). note: for all sequencer modes, the default exit state upon completion of all conversions is sleep. in sequencer mode 1, however, continuous conversion operation (ctrl1:scycle=0) and continuous sin - gle-cycle conversion operation (ctrl1:scycle=1 and ctrl1:contsc=1) are running continuously and must be terminated with the mode exit sequence. table 4. command byte definition table 5. command byte decoding b7 (msb) b6 b5 b4 b3 b2 b1 b0 conversion command 1 0 mode1 mode0 rate3 rate2 rate1 rate0 register read/write 1 1 rs4 rs3 rs2 rs1 rs0 r/ w bit name description mode[1:0] the mode bits are used to set the functional operation of the MAX11253 according to the following decoding. mode1 mode0 description 0 0 unused 0 1 power-down performed based on the ctrl1:pd[1:0] setting 1 0 calibration performed based on the ctrl1:cal[1:0] setting 1 1 sequencer mode. the operation is based on the coniguration of the seq register rate[3:0] these bits determine the conversion speed of the MAX11253. the decoding is shown in table 1. rs[4:0] register address as shown in table 8. r/ w the r/ w bit enables either a read or a write access to the address speciied in rs[4:0]. if r/ w is set to 0, then data is written to the register. if the r/ w bit is set to 1, then data is read from the register. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 22 downloaded from: http:///
mode change to change sequencer modes or to update the seq regis - ter, program the following sequence: 1) perform sequencer mode exit (see the mode exit section). 2) set up the following registers: seq, ctrl1. a. set seq:mode[1:0] to select the new sequencer mode b. set ctrl1:pd[1:0] to standby or sleep state to set the desired exit state if a conversion com - mand with mode[1:0] set to 01 is issued during the conversion. 3) write the command byte (see table 4 ). a. set mode[1:0] of the command byte to 11 (sequencer mode) 4) wait for stat:pdstat[1:0] = 00 to confirm conversion mode. sequencer mode 1single-channel conver- sion with gpo control and mux delays this mode is used for single-channel conversions where the sequencer is disabled. figure 9 illustrates the timing. to support high-impedance source networks, the conver - sion delay (seq:mdren) feature must be enabled. the states of the gpo and gpio pins are configured using the gpo_dir and gpio_ctrl registers and can be modi - fied anytime during mode 1 operation. the values of the chmap0/chmap1 registers and delay:gpo[7:0] bits are ignored in this mode. programming sequence mode entry 1) set up the following registers: seq, delay, ctrl1, gpo_dir, gpio_ctrl. a. seq:mode[1:0] = 00 for sequencer mode 1 b. seq:mux[2:0] to select the channel for conversion c. enable seq:mdren to delay conversion start to allow for input settling. set delay:mux[7:0] to the desired conversion delay d. set ctrl1:scycle for either single cycle (no latency) or continuous conversion e. if single-cycle conversion is selected, set ctrl1:contsc to 1 if continuous single-cycle conversion is desired f. set ctrl1:pd[1:0] to standby or sleep state to set the desired exit state if a conversion command with mode[1:0] set to 01 is issued during the conversion g. set register gpo_dir and, if desired, gpio_ctrl to enable or disable the desired gpo and gpio pins 2) write a conversion command (see table 4 , command byte definition ). a. set data rate using bits rate[3:0] of the command byte b. set mode[1:0] of the command byte to 11 for sequencer mode 3) monitor rdyb for availability of conversion results in the data register (see figure 4 for rdyb timing). mode exit 1) in single-cycle conversion mode (ctrl1:scycle =1) the sequencer exits into sleep state. 2) in continuous conversion mode (ctrl1: scycle=0 or (ctrl:scycle=1 and ctrl1:contsc =1)), conversions continue nonstop until the mode is exited. to interrupt and exit continuous conversion or con - tinuous single-cycle conversion follow the changing sequencer modesmode exit section to put the part into standby or sleep state based on ctrl1:pd[1:0] set in step 1(f) of mode entry section. changing input channel during continuous single-cycle conversion in mode 1 1) issue a conversion command with mode[1:0] set to 01 to exit the conversion process to standby or sleep state (see the changing sequencer modesmode exit section). 2) monitor stat:pdstat = 10 or 01 to confirm exit to standby or sleep state. 3) set seq:mux[2:0] to select the new channel for con - version 4) write a conversion command (see table 4 ) and set mode[1:0] of command byte to 11 sequencer mode 2 C multichannel scan with gpo control and mux delays this mode is used to sequentially convert a programmed set of channels in a preset order. figure 10 illustrates the timing. the states of the gpo and gpio pins are configured using the gpo_dir and gpio_ctrl registers and can be modi - fied anytime during mode 2 operation. in mode 2, reg - ister bits chmap0:chn_ord[2:0], chmap1:chn_ ord[2:0], chmap0:chn_en, and chmap1:chn_en are used to select channels and conversion order. bits delay:gpo[7:0], chmap0:chn_gpo[2:0], chmap0:chn_gpoen, chmap1:chn_gpo[2:0], and chmap1:chn_gpoen are ignored in this mode. the bit ctrl1:contsc is ignored and bit ctrl1:scycle = 0 is invalid in this mode. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 23 downloaded from: http:///
programming sequencemode entry 1) set up the following registers: seq, chmap0, chmap1, delay, gpo_dir, gpio_ctrl, ctrl1 a. seq:mode[1:0] = 01 for sequencer mode 2 b. if desired set seq:rdyben to 1 to signal data ready only when all channel conversions are com - pleted c. enable seq:mdren to delay conversion start to allow for input settling. set delay:mux[7:0] to the desired conversion delay d. set chmap0 and chmap1 to select the channels and channel order for conversion e. set ctrl1:pd[1:0] to standby or sleep state to set the desired exit state if a conversion com - mand with mode[1:0] set to 01 is issued during the conversion f. set register gpo_dir and gpio_ctrl to enable or disable the desired gpo and gpio pins g. set ctrl1:scycle = 1 for single-cycle conver - sion mode 2) write a conversion command (see table 4 ). a. set data rate using bits rate[3:0] of the command byte b. set mode[1:0] of the command byte to 11 3) monitor rdyb (if seq:rdyben=0) and bits stat:srdy[5:0] for availability of per channel conver - sion results in data[x] registers. mode exit 1) this mode exits to sleep state upon completion of sequencing all channels 2) to interrupt current sequencing perform mode exit, see the changing sequencer modesmode exit section. this device is put in standby or sleep state based on ctrl1:pd[1:0] set in step 1(e) of mode entry section. sequencer mode 3 C scan, with sequenced gpo controls this mode is used to sequentially convert a programmed set of channels in a preset order and sequence the gpo/gpio pins concurrently. the gpo/gpio pins are used to bias external circuitry such as bridge sensors; the common reference (gpognd) is typically ground. after all channel conversions have completed, the MAX11253 automatically powers down into sleep mode. figure 11 illustrates the sequencer mode 3 timing diagram for a three-channel scan. as long as ctrl3:gpo_mode is set to 1, registers gpo_dir and gpio_ctrl are ignored in this mode, as the gpo/gpio pins are controlled by the sequencer. figure 9. sequencer mode 1 timing diagram figure 10. sequencer mode 2 timing diagram sequencer mode 1 del channel conversion seq:mdren ? delay:mux seq:mux[2:0] sequencer mode 2 seq:mdren ? delay:mux chanmap:ord[2:0] = 001 del channel conversion del del del del del channel conversion channel conversion channel conversion channel conversion channel conversion chanmap:ord[2:0] = 010 seq:mdren ? delay:mux seq:mdren ? delay:mux chanmap:ord[2:0] = 011 seq:mdren ? delay:mux chanmap:ord[2:0] = 100 seq:mdren ? delay:mux chanmap:ord[2:0] = 101 seq:mdren ? delay:mux chanmap:ord[2:0] = 110 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 24 downloaded from: http:///
if ctrl3:gpo_mode is set to 0, the gpo/gpio pins are directly controlled by the gpo_dir and gpio_ctrl registers and are not controlled by the sequencer. programming sequence mode entry 1) set up the following registers: seq, chmap0, chmap1, delay, ctrl1, ctrl3 a. seq:mode[1:0]=10 for sequencer mode 3 b. if desired, set seq:rdyben to 1 to signal data ready only when all channel conversions are com - pleted c. enable seq:mdren if conversion start is to be delayed to allow for input settling. set delay:mux[7:0] to the desired conversion delay d. set ctrl3:gpo_mode to 1 to enable gpo/ gpio sequencing e. set chmap0 and chmap1 to enable the chan - nels for conversion and to set the channel con - version order. map the corresponding gpo/gpio pins to a channel. f. enable seq:gpodren to add a delay before the multiplexer selects this channel for conversion. set delay:gpo to a delay value sufficient for the bias to settle. g. set ctrl1:pd[1:0] to standby or sleep state to set the desired exit state if a conversion command with mode[1:0] set to 01 is issued during the conversion h. set ctrl1:scycle = 1 for single conversion mode 2) write the conversion command (see table 4 ) a. set the data rate using bits rate[3:0] of the com - mand byte b. set mode[1:0] of command byte to 11 3) monitor rdyb (if seq:rdyben = 0) and bits stat:srdy[5:0] for availability of per channel con - version results in data[x] registers. mode exit 1) this mode exits to sleep state upon completion of sequencing all channels and gpo/gpio pins. 2) to interrupt the current sequencing, perform mode exit. see the changing sequencer modesmode exit section. this puts the part in standby or sleep state based on ctrl1:pd[1:0] set in step 1(g) of mode entry. the bit ctrl1:contsc is ignored and bit ctrl1:scycle = 0 is invalid in this mode. figure 11. sequencer mode 3 timing diagram for a three-channel scan sequencer mode 3 timing del2 tconvert delay:gpo gpo/gpio activated scan channel #1 del2 gpo/gpio activated conversion starts chanmap:ord[2:0] = 001 chanmap:ord[2:0] = 010 del2 gpo/gpio activated conversion starts chanmap:ord[2:0] = 011 del1 tconvert tconvert (tconvert and del1) end trigger mux selects channel (tconvert and del1) end trigger mux selects channel mux selects channel conversion starts conversion ends seq:mdren ? delay:mux scan channel #2 scan channel #3 conversion ends conversion ends del1 C programmed delay using bits delay:gpo[7:0] to provide sufficient settling time for the sensor before the first channel is converted. del2 C programmed delay using bits delay:mux[7:0] for sensor and analog input settling after the multiplier selects the channel for conversion. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 25 downloaded from: http:///
operating examplesfrom full power-down to mode 3 in this example, channels 0, 1, and 2 are configured for conversion in mode 3. channel 0 is configured last in the scan order and the gpio0 is mapped to this channel. channel 1 is configured first in the scan order and gpo1 is mapped to this channel. channel 2 is configured sec - ond in the scan order and gpo0 is mapped to this chan - nel. channels 0, 1, and 2 are enabled for scan and gpo/ gpio switching is also enabled. the rdyben is not set which generates a rdyb transition after each channel is converted. the pga is configured for a gain of 128 and the data rate is 6,400sps in single-cycle mode. the mux delays are enabled for all used channels and the gpo/ gpio delays are disabled. reference spi command sequence section. error checking sequencer mode 3 the MAX11253 perform checks on registers chmap0 and chmap1. error flags are set when invalid values are set: stat:gpoerr is set when more than one input chan - nel is mapped to the same gpo/gpio pin. stat:orderr is set when chn_ord is set as 000 or 111 and channel n is enabled using chmapx:chn_en. supplies and power-on sequence the MAX11253 requires two power supplies, avdd and dvdd. these power supplies can be sequenced in any order. the analog supply (avdd) powers the analog inputs and the modulator. the dvdd supply powers the spi interface. the low-voltage core logic can either be powered by the integrated ldo (default) or via dvdd. figure 12 shows the two possible schemes. capreg denotes the internally generated supply voltage. if the ldo is used, the dvdd operating voltage range is from 2.0v to 3.6v. if the core logic is directly powered by dvdd (dvdd and capreg connected together), the dvdd operating voltage range is from 1.7v to 2.0v. figure 12. MAX11253 digital power architecture analog 2v digital logic digital interface inputs and outputs ldo capreg 220nf0603 x7r dgnd avdd dvdd MAX11253 analog 2v digital logic digital interface inputs and outputs ldo capreg avdd dvdd MAX11253 dvdd operating between 2.0v to 3.6v ldo enabled (set ctrl2:ldoen = 1) and bypass capreg to dgnd with 220nf dvdd operating between 1.7v to 2.0v ldo disabled (set ctrl2:ldoen = 0) and connect capreg to dvdd at board level MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 26 downloaded from: http:///
spi command sequence spi transactions description csb=0; spi=0xd012; csb=1; write to seq register set mux to 0b000, mode to 0b10, gpodren to 0b0, mdren to 0b1, rdyben to 0b0 csb=0; spi=0xcaf000; csb=1; write to delay register set mux[7:0] to 0xf0, gpo[7:0] to 0x00 csb=0; spi=0xc65c; csb=1; write to ctrl3 register set gpo_mode to 0b1, all others to the default value; csb=0; spi=0xce0b274f; csb=1 write to chmap0 register ch2=0x0b: ch2_gpo=0b00, ch2_ord=0b010, ch2_en=0b1, ch2_gpoen=0b1 ch1=0x27: ch1_gpo=0b01, ch1_ord=0b001, ch1_en=0b1, ch1_gpoen=0b1 ch0=0x4f: ch0_gpo=0b10,ch0_ord=0b011, ch0_en=0b1, ch0_gpoen=0b1 csb=0; spi=0xc43f; csb=1; write to ctrl2 register set pga gain to 0b111, ldoen=0b1, lpmode=0b1, pgaen=0b1; csb=0; spi=0xbe; csb=1; convert using sequencer mode, data rate selected is 6,400 sps; wait rdyb negative edge transition from 1 to 0 indicates conversion completed and data register ready for read csb=0; spi=0xd30000; csb=1; read register data1; wait rdyb negative edge transition from 1 to 0 indicates conversion completed and data register ready for read csb=0; spi=0xd50000; csb=1; read register data2 wait rdyb negative edge transition from 1 to 0 indicates conversion completed and data register ready for read csb=0; spi=0xd10000; csb=1; read register data0; stop mode activity is completed. the MAX11253 powers down into sleep state waiting for the next command MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 27 downloaded from: http:///
power-on reset and undervoltage lockout a global power-on reset (por) is triggered until avdd, dvdd, and capreg cross a minimum threshold voltage (v lh ), as shown in figure 13 . to prevent ambiguous power-supply conditions from causing erratic behavior, voltage detectors monitor avdd, dvdd, and capreg and hold the MAX11253 in reset when supplies fall below v hl (see figure 13 ). the ana - log undervoltage lockout (avdd uvlo) prevents the adc from converting when avdd falls below v hl . the capreg uvlo resets and prevents the low-voltage digital logic from operating at voltages below v hl . dvdd uvlo thresholds supersede capreg thresholds when capreg is externally driven. figure 14 shows a flow dia - gram of the por sequence. glitches on supplies avdd, dvdd, and capreg for durations shorter than t p are suppressed without triggering por or uvlo. for glitch durations longer than t p , por is triggered within t del seconds. see the electrical characteristics table for val - ues of v lh , v hl , t p , and t del . power-on reset timing power-on reset is triggered during power-up and under - voltage conditions as described above. completion of the por process is monitored by polling stat:pdstat[1:0] = 10 for standby state (see figure 15 ). resethardware reset using rstb the MAX11253 features an active-low rstb pin to per - form a hardware reset. pulling the rstb pin low stops any conversion in progress, reconfigures the internal registers to the power-on reset state and resets all digital filter states to zero. after the reset cycle is completed, the MAX11253 remains in standby state and awaits further commands. software reset the host can issue a software reset to restore the default state of the MAX11253. a software reset sets the interface registers back into their default states and resets the inter - nal state machines. however, a software reset does not emulate the complete por or hardware reset sequence. two spi transactions are required to issue a software reset: first set ctrl1:pd[1:0] to 11 (reset). then issue a conversion command with mode[1:0] set to 01. to confirm the completion of the reset operation, stat:pdstat and stat:inreset must be monitored. figure 16 shows the state transition for the reset com - mand and the relative timing of stat register update. during reset, inreset = 1 and pdstat= 11. the spi interface cannot be written until MAX11253 enters standby state where pdstat = 10. to confirm com - pletion of the reset command, monitor for inreset = 0 and pdstat = 10.0 table 6 summarizes the maxi - mum delay for reset operation. figure 13. undervoltage lockout characteristic voltage levels and timing avdd dvdd capreg porb t del v hys v hl v lh t p t del t p MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 28 downloaded from: http:///
table 6. maximum delay time for mode transitions * the commands are deined as follows: sleep: set ctrl1:pd[1:0] to 01; issue a conversion command with mode[1:0] set to 01 standby: set ctrl1:pd[1:0] to 10; issue a conversion command with mode[1:0] set to 01 reset: set ctrl1:pd[1:0] to 11; issue a conversion command with mode[1:0] set to 01 convert: any conversion command with mode[1:0] set to 11 por: power-on reset during initial power-up or uvlo rstb: hardware reset with rstb pin ? see the electrical characteristics for t pupslp and t pupsby command issued* MAX11253 state before command command interpretation maximum delay time to next state ? MAX11253 state after command sleep reset command ignored 0 reset sleep command ignored 0 sleep standby MAX11253 powers down into sleep mode 20ms sleep standby (fast) issue a conversion command and then monitor stat:pdstat[1:0] for change of mode; then send conversion command with mode[1:0] set to 01 15s sleep calibration calibration stops, MAX11253 powers down into sleep mode 3s sleep conversion conversion stops, MAX11253 powers down into sleep mode 3s sleep convert sleep mode change from sleep to conversion sat: pdstat changes to 00 t pupslp + 3s conversion standby standby to conversion t pupsby + 3s conversion standby reset command ignored 0 reset sleep MAX11253 changes to standby 20ms standby sleep (fast) issue a conversion command and then monitor stat:pdstat[1:0] for change of mode; then send conversion command with mode[1:0] set to 01 85s standby standby command ignored 0 standby calibration calibration stops 3s standby conversion conversion stops 3s standby reset reset command ignored 0 reset sleep command ignored 0 sleep standby register values reset to default 28ms standby calibration calibration stops, register values reset to default 6s standby conversion conversion stops, register values reset to default 6s standby por off from complete power-down to standby mode 10ms standby rstb any from any state to standby mode 10ms standby MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 29 downloaded from: http:///
figure 15. power-on reset and pdstat timing figure 14. MAX11253 uvlo and por flow diagram v dvdd 11 stat:pdstat=xx 10 (standby) in power-on reset out of power-on reset serial interface read only serial interface available for both read and write capreg uvlo triggered? power-on reset for 2v digital logic yes analog reset no avdd uvlo triggered? yes no oscillator reset dvdd uvlo triggered? power-on reset for digital logic and interface yes no power-on MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 30 downloaded from: http:///
power-down states to reduce overall power consumption, the MAX11253 features two power-down states: standby and sleep. in sleep mode all circuitry is powered down, and the supply currents are reduced to leakage currents. in standby mode the internal ldo and a low-frequency oscillator are powered up to enable fast startup. after por or a hardware reset the MAX11253 is in standby mode until a command is issued. changing power-down states mode transition times are dependent on the current mode of operation. stat:pdstat is updated at the end of all mode changes and is a confirmation of a completed trans - action. the MAX11253 does not use a command fifo or queue. the user must confirm the completed transaction by polling stat:pdstat after the expected delay, as described in table 6 . once the transition is complete, it is safe to send the next command. verify that stat:pdstat indicates the desired state before issuing a conversion command. writes to any ctrl register during a conversion aborts the conversion and returns the MAX11253 to standby state. sleep state to standby state (fast) 1) set ctrl1:pd[1:0] = 10 for standby state. 2) set seq:mode[1:0] = 00 for sequencer mode 1 3) issue a conversion command with mode[1:0] set to 11. 4) monitor stat:pdstat[1:0] = 00 for active state. 5) write the conversion command with mode[1:0] set to 01. 6) monitor stat:pdstat = 10 for completion. standby state to sleep state (fast) 1) set ctrl1:pd[1:0] = 01 for standby state. 2) set seq:mode[1:0] = 00 for sequencer mode 1 3) issue a conversion command with mode[1:0] set to 11. 4) monitor stat:pdstat[1:0] = 00 for active state. 5) write the conversion command with mode[1:0] set to 01. 6) monitor stat:pdstat = 01 for completion. calibration two types of calibration are available: self calibration and system calibration. self calibration is used to reduce the MAX11253s gain and offset errors during changing operating conditions such as supply voltages, ambi - ent temperature, and time. system calibration is used to reduce the gain and offset error of the entire signal path. this enables calibration of board level components and the integrated pga. system calibration requires the MAX11253s inputs to be reconfigured for zero scale and full scale during calibration. the gpo/gpio pins can be used for this purpose. see figure 17 for details of the calibration signal flow. the calibration coefficients are stored in the registers scoc, scgc, soc and sgc. data written to these registers is stored within the spi domain and copied to internal registers before a conversion starts to process the raw data (see figure 17 ). an internal or system cali - bration only updates the internal register values and does not alter the contents stored in the spi domain. the bit ctrl3:calregsel decides whether the internal con - tents or the contents stored in the spi domain are read back during a read access of these registers. figure 16. stat:inreset and stat:pdstat timing reset command stat:inreset 11 stat:pdstat = 00/10' 10 idle serial interface is read only during this period serial interface is avaiable for both read and write command latched MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 31 downloaded from: http:///
figure 17. calibration flow diagram subtract scoc multiply scgc subtract soc multiply sgc data nosco=0 noscg=0 t f t f nosyso=0 t f nosysg=0 f t status reg cal block spi block unipolar x2 f t limiter scoc_internal scgc_internal soc_internal sgc_internal 24 24 24 24 raw result final result MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 32 downloaded from: http:///
bits nosco, noscg, nosyso, nosysg enable or disable the use of the individual calibration coefficients during data processing. see figure 17 , calibration flow diagram . self-calibration the self-calibration is an internal operation and does not disturb the analog inputs. the self-calibration command can only be issued in sequencer mode 1 (seq:mode[1:0] = 00). self-calibration is accomplished in two indepen - dent phases, offset and gain. the first phase disconnects the inputs to the modulator and shorts them together internally to develop a zero-scale signal. a conversion is then completed and the results are post-processed to generate an offset coefficient which cancels all internally generated offsets. the second phase connects the inputs to the reference to develop a full-scale signal. a conver - sion is then completed and the results are post-processed to generate a full-scale coefficient, which scales the converters full-scale analog range to the full-scale digital range. the entire self-calibration sequence requires two inde - pendent conversions, one for offset and one for full scale. the conversion rate is 50sps in the single-cycle mode. this rate provides the lowest noise and most accurate calibrations. the self-calibration operation excludes the pga. a sys - tem level calibration is available in order to calibrate the pga signal path. a self-calibration is started as follows: set ctrl1:cal[1:0] to 00 (self-calibration). then issue a conversion com - mand with the mode[1:0] bits set to 10 (calibration). a self-calibration requires 200ms to complete. system calibration this mode is used when calibration of board level compo - nents and the integrated pga is required. the system cal - ibration command is only available in sequencer mode 1. a system calibration requires the input to be configured to the proper level for calibration. the offset and full-scale system calibrations are, therefore, performed using sepa - rate commands. the channel selected in the seq:mux bits is used for system calibrations. to perform a system offset calibration, the inputs must be configured for zero scale. the inputs do not necessarily need to be shorted to 0v as any voltage within the range of the calibration registers can be nulled in this calibration. a system offset calibration is started as follows: set ctrl1:cal[1:0] to 01 (system offset calibration). then issue a conversion command with the mode[1:0] bits set to 10 (calibration). the system offset calibration requires 100ms to complete. to perform a system full-scale calibration, the inputs must be configured for full scale. the input full-scale value does not necessarily need to be equal to v ref since the input voltage range of the calibration registers can scale up or down appropriately within the range of the calibration registers. a system full-scale calibration is started as follows: set ctrl1:cal[1:0] to 10 (system full-scale calibration). then issue a conversion command with the mode[1:0] bits set to 10 (calibration). the system full-scale calibra - tion requires 100ms to complete. the gpo/gpio pins can be used during a system cali - bration. all four calibration registers (soc, sgc, scoc, and scgc) can be written by the host to store special calibra - tion values. the new values will be copied to the internal registers at the beginning of a new conversion. gpios the MAX11253 provides two general-purpose input/out - put ports that are programmable through the gpio_ctrl register. enable the gpio pins by setting bits gpio1_en and gpio0_en, respectively. set the dir bits to select the pins to be configured as inputs or outputs. all pins are inputs by default. when programmed as output, set the dio bits to set the pin state to 0 or 1. conversion synchronization using sync pin and external clock the sync pinin conjunction with an external clock can be used to synchronize the data conversions to external events. set gpio_ctrl:gpio1_en to 0 and gpi_ctrl:gpio0_en to 0 to configure the gpio1/ sync and gpio0/clk pins. configure sync mode by set - ting ctrl3:sync_mode to 1 and external clock mode by setting ctrl2:extclk to 1. the synchronization mode is used to detect if the cur - rent conversions are synchronized to a continuous pulse signal with a period greater than the data rate. ideally, the frequency of the synchronization signal is an integer multiple of the conversion rate. the synchronization mode records the number of device master clock cycles between a rdyb assertion and the rising edge of the next sync pulse. at the following sync pulse, the number of master clock cycles between a rdyb assertion and the rising edge of the sync pulse is evaluated again and com - pared to the recorded value. if the new number of master clock cycles differs by more than one from the recorded MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 33 downloaded from: http:///
value, the conversion in progress is stopped, the digital filter contents are reset, and a new conversion starts. as the digital filter is reset, the full digital filter latency is required before valid results are available. if the new mas - ter clock count is within the 1 count limit, the conversions continue uninterrupted. figure 18 shows the timing relationship between the MAX11253 master clock and the sync signal. due to startup delays, any sync pulses before the first rdyb assertion (low-going edge) are ignored. the first rising edge on the sync pin after a rdyb assertion establishes the relationship between the sync signal and the conver - sion timing. components of the adc modulator modulator digital overrange the output of the sinc filter is monitored for overflow. when sinc filter overflow is detected, the stat:dor bit is set to 1 and a default value is loaded into the data register depending on the polarity of the overload. a posi - tive overrange causes 0x7fff to be written to the data register. a negative overrange causes 0x8000 to be writ - ten to the data register. see table 7 . sync signal rdyb first conversion ready n ... clk > 2 x t clk ignored first valid sync device initiates a reset and restarts conversions when n and n differ by more than 1clk count. otherwise conversions continue uninterrupted. t clk > 2 x t clk n figure 18. timing relationship between sync signal, external clock and rdyb table 7. analog overrange behavior for different operating conditions and modes the data values shown are for bipolar ranges with twos complement number format. v ovrrng is the overrange volt - age value typically > 120% of v ref . stat register input voltage aor dor data -v ref < v in < v ref 0 0 result v ref < v in < v ovrrng 1 0 result -v ovrrng < v in < -v ref 1 0 result v in > v ovrrng 1 1 0x7fff v in < -v ovrrng 1 1 0x8000 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 34 downloaded from: http:///
modulator analog overrange the modulator analog overrange is used to signal the user that the input analog voltage has exceeded preset limits defined by the modulator operating range. these limits are approximately 120% of the applied reference voltage. when analog overrange is detected the stat:aor bit is set to 1 after data is updated. the aor bit will always correspond to the current value in the data register. see table 7 . sinc filtert he digital filter is a mode-configurable digital filter and decimator that processes the data stream from the fourth order delta-sigma modulator and implements a fifth order sinc function with an averaging function to produce a 24-bit wide data stream. the sinc filter allows the MAX11253 to achieve very high snr. the bandwidth of the fifth order sinc filter is approximately twenty percent of the data rate. see figures 19 and 20 for the filter response of 64ksps and 4ksps, respectively. see figure 21 for the bandwidth of the individual signal stages. applications information connecting an external 1.8v supply to dvdd for digital i/o and digital core the voltage range of the dvdd i/o supply is specified from 2.0v to 3.6v if the internal ldo is used to power the digital core. if a lower i/o supply voltage is desired, the internal ldo can be disabled, and dvdd and capreg can be connected together as shown in figure 22 . in this mode of operation, dvdd can vary from 1.7v to 2.0v. the internal ldo must be disabled by setting ctrl2:ldoen to 0. split supplies the MAX11253 supports unipolar and split analog power supplies for input range flexibility. using a split analog supply enables sampling below ground reference. the true bipolar input range is up to 1.8v. see figure 3 for analog input voltage range for both unipolar and split supplies. sensor fault detection the MAX11253 includes a 1a current source and a 1a current sink. the source pulls current from avdd to ain_p and sink from ain_n to avss. the currents are enabled by register bit ctrl3:cssen. these currents are used to detect damaged sensors in either open or shorted state. the current sources and sinks are func - tional over the normal input operating voltage range, as specified. these currents are used to test sensors for functional operation before taking measurements on that input channel. with the source and sink enabled, the currents flow into the external sensor circuit and measurement of the input voltage is used to diagnose sensor faults. a full-scale reading could indicate a sensor is open circuit or overloaded or that the adcs reference is absent. if a zero-scale is read back, this may indicate the sensor is short-circuited. figure 19. digital filter frequency response for 64ksps continuous data rate and 12.8ksps single-cycle data rate figure 20. digital filter frequency response for 4ksps single-cycle data rate sinc5 filter, normal mode rejection data rate 64000.0sps frequency (hz) gain (db) x 10 4 2 4 -20 -10 0 0 6 -40-60 -80 -100-120 -140 -160 -180 -200 -30-50 -70 -90 -110-130 -150 -170 -190 8 10 12 sinc5 filter, normal mode rejection single cycle data rate 4000.0sps frequency (hz) gain (db) x 10 4 1 -20 -10 0 0 2 -40-60 -80 -100-120 -140 -160 -180 -200 -30-50 -70 -90 -110-130 -150 -170 -190 3 4 5 6 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 35 downloaded from: http:///
figure 21. signal path block diagram including bandwidth of each stage MAX11253 c ref 1nf c0g ain5p ain5n gpo0 1nf c0g gpo1 ain0n ain0p 10nf refn refp 1f avdd 2.7v to 3.6v 1.7v to 2.0v gpognd capp capn 1nf c0g rdyb dout din csb dvdd rstb sclk 1fx7r capreg dgnd avss figure 22. application diagram for 1.8v dvdd delta-sigma adc pga digital filter n 16 g=128 sn = 5nv/ hz analog filter n bw3 neb 10nf 23k 36k 1nf 230k 361k 100pf 2.3m 3.6m bw3 neb 10nf 21k 33k 1nf 69k 108k 100pf 73k 115k neb2 = /2 x bw3 neb1 = /2 x bw3 neb3 = 0.215 x fdata 64ksps = 13.2khz bw3 bw3 fdata neb3 bw3 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 36 downloaded from: http:///
register map legend: cnv in progress column C behavior during conversion: cnv C normal read/write activities are available. cs C writes to these registers immediately abort conversion in progress and the MAX11253 enters standby state. ig C no changes, write is ignored. retention column C behavior during sleep mode: r C the value of the register is retained. m C only bits in < > are retained. others are cleared. the address column shows the register address as used in the command byte definition (see table 4 ). MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 37 downloaded from: http:///
table 8. register map name r/w cnv in progress retention address (rs[4:0]) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stat r m 0 inreset scanerr refdet orderr gpoerr error sysgor dor aor rate3 rate2 rate1 rate0 mstat ctrl1 r/w cs r 1 cal1 cal0 pd1 pd0 u/ b format scycle contsc ctrl2 r/w cs r 2 extclk cssen ldoen lpmode pgaen pgag2 pgag1 pgag0 ctrl3 r/w cs r 3 gpo_mode sync_mode calregsel nosysg nosyso noscg nosco gpio_ctrl r/w cnv r 4 gpio1_en gpio0_en dir1 dir0 dio1 dio0 delay r/w ig r 5 mux[7:0] gpo[7:0] chmap1 r/w ig r 6 ch5_gpo1 ch5_ gpo0 ch5_ord2 ch5_ord1 ch5_ord0 ch5_en ch5_gpoen ch4_gpo1 ch4_ gpo0 ch4_ord2 ch4_ord1 ch4_ord0 ch4_en ch4_gpoen ch3_gpo1 ch3_gpo0 ch3_ord2 ch3_ord1 ch3_ord0 ch3_en ch3_gpoen chmap0 r/w ig r 7 ch2_gpo1 ch2_gpo0 ch2_ord2 ch2_ord1 ch2_ord0 ch2_en ch2_gpoen ch1_gpo1 ch1_gpo0 ch1_ord2 ch1_ord1 ch1_ord0 ch1_en ch1_gpoen ch0_gpo1 ch0_gpo0 ch0_ord2 ch0_ord1 ch0_ord0 ch0_en ch0_gpoen seq r/w cnv r 8 mux2 mux1 mux0 mode1 mode0 gpodren mdren rdyben gpo_dir r/w cnv r 9 gpo1 gpo0 soc r/w ig r 10 d[23:0] sgc r/w ig r 11 d[23:0] scoc r/w ig r 12 d[23:0] scgc r/w ig r 13 d[23:0] data0 r r 14 d[15:0] data1 r r 15 d[15:0] data2 r r 16 d[15:0] data3 r r 17 d[15:0] data4 r r 18 d[15:0] data5 r r 19 d[15:0] MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 38 downloaded from: http:///
register deinitions stat: status register (read) bit name inreset srdy5 srdy4 srdy3 srdy2 srdy1 srdy0 default 0 0 0 0 0 0 0 0 bit name scanerr refdet orderr gpoerr error sysgor dor aor default 0 1 0 0 0 0 0 0 bit name rate3 rate2 rate1 rate0 pdstat1 pdstat0 mstat rdy default 0 0 0 0 0 0 0 0 this register provides the functional status of the MAX11253. bit name description inreset this bit is set to 1 to indicate that the MAX11253 is in reset. srdy[5:0] this bit is set to 1 in sequencer modes 2 and 3 to indicate that a new conversion result is available from the channel indicated by the srdy bit position. a complete read of the data register associated with the srdy bit will reset the bit to 0. at the start of a scan mode these bits are reset to 0. scanerr this bit is set to 1 if sequencer mode 2 or 3 is selected and no channels or invalid channel numbers (000 or 111) are enabled in the chmap1 or chmap0 register. until scanerr is cleared, conversion commands are aborted. refdet this bit is set to 1 if a proper reference voltage is detected and 0 if a proper reference voltage is missing. in sleep or standby mode the value of this bit is 0. the trigger level for this bit is v ref < 0.35v. this error does not inhibit normal operation and is intended for status only. the value of this status bit is valid within 30s after a conversion start command and is invalid when not in conversion. orderr this bit is set to 1 if two or more chx_ord bits decode to the same scan sequence order and are also enabled. this bit is also set to 1 in the case when a channel is enabled for scan with chx_en=1 and chx_ ord[2:0] = 000 or 111. the chx_ord[2:0] values of 000 and 111 are not allowed as order of an enabled channel. the allowable orders are 001, 010, 011, 100, 101, 110. the MAX11253 remains in standby state until this error is removed. the channel order must be strictly sequential and no missing numbers are allowed. for instance, if 4 channels are enabled then the order must be 001, 010, 011, 100. any other order is lagged as orderr and the MAX11253 remains in standby mode. gpoerr this bit is set to 1 if more than one input channel is mapped to the same gpo/gpio pin, and chx_gpoen is enabled for more than one channel. the MAX11253 remains in standby state until this error is removed. error this bit is set to 1 to indicate invalid coniguration states. this bit is set if cal[1:0] is progr ammed to 11 which is an invalid state. this bit is set if ctrl1:scycle = 0 for scan modes 2 and 3. this error puts the MAX11253 into standby mode. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 39 downloaded from: http:///
stat: status register (read) (continued) bit name description sysgor this bit is set to 1 to indicate that a system gain calibration results in an overrange condition of the calibration coeficient. the scgc calibration coeficient is set to the maximum value of 1.9999999. dor this bit is set to 1 to indicate that the conversion result has exceeded the maximum or minimum value of the converter and that the result has been clipped or limited to the maximum or minimum value. when set to 0 the conversion result is within the full-scale range of the inputs. aor this bit is set to 1 to indicate that the modulator detected an analog overrange condition by having the input signal level greater than the reference voltage. this check for overrange includes the pga gain. rate[3:0] these bits indicate the conversion rate that corresponds to the result in the data registers or the rate that was used for calibration coeficient calculation. the corresponding rate[3:0] is only valid until the dat a registers are read. the decoding of rate[3:0] is shown in table 1. pdstat[1:0] these bits indicate the state of the MAX11253. see table 6 for transition times. pdstat1 pdstat0 description 0 0 conversion 0 1 sleep 1 0 standby (default) 1 1 reset mstat this bit is set to 1 to indicate when a signal measurement is in progress. this indicates that a conversion, self-calibration, or system calibration is in progress and that the modulator is busy. when the modulator is not converting, this bit will be set to 0. rdy this bit is set to 1 to indicate that a new conversion result is available in sequencer mode 1. a complete read of the corresponding data register will reset this bit to 0. this bit is invalid in sequencer mode 2 or 3. the function of this bit is redundant and is duplicated by the rdyb pin. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 40 downloaded from: http:///
ctrl1: control register 1 (read/write) default = 0x02l bit name cal1 cal0 pd1 pd0 u/ b format scycle contsc default 0 0 0 0 0 0 1 0 this register controls the selection of operational modes and conigurations. bit name description cal[1:0] the calibration bits control the type of calibration performed when a calibration command byte is issued: cal1 cal0 description 0 0 performs a self-calibration 0 1 performs a system-level offset calibration 1 0 performs a system-level full-scale calibration 1 1 reserved. do not use. pd[1:0] selects the power-down state to be executed. the MAX11253 enters the selected power-down state after a conversion command with mode[1:0] set to 01 is written. the state is decoded as below: pd1 pd0 description 0 0 nop (default) 0 1 sleep 1 0 standby 1 1 reset u/ b the unipolar/bipolar bit controls the input range. a 1 selects unipolar input range and a 0 selects bipolar input range. format the format bit controls the digital format of the bipolar range data. a 0 selects twos complement and a 1 selects offset binary format of the bipolar range. the data for unipolar range is always formatted in offset binary format. scycle the single-cycle bit selects either no-latency single conversion mode or continuous conversion in sequencer mode 1. a 1 selects single-cycle mode where a no-latency conversion is followed by a power-down to sleep mode. a 0 selects continuous conversion mode with a latency of 5 conversion cycles for iltering. the rdyb pin goes low when valid/settled data is available. only scycle = 1 i s valid in sequencer mode 2 and 3. contsc the continuous single-cycle bit selects between single or continuous conversions while operating in single-cycle mode in sequencer mode 1. a 1 selects continuous conversions and a 0 selects a single conversion. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 41 downloaded from: http:///
ctrl2: control register 2 (read/write) default = 0x20 bit name extclk cssen ldoen lpmode pgaen pgag2 pgag1 pgag0 default 0 0 1 0 0 0 0 0 this register controls the selection and coniguration of optional functions. bit name description extclk external clock mode is enabled by setting this bit to 1. in this mode, the internal oscillator is bypassed and the gpio0/clk pin is conigured as external clock input. cssen setting this bit to 1 enables the current source and current sink on the analog inputs to detect sensor opens or shorts. ldoen set this bit to 1 to enable the internal ldo. set this bit to 0 when driving the capreg pin externally with a 1.8v supply. when driving the capreg pin with external supply, the user must ensure that the capreg pin is connected to the dvdd pin. lpmode pga low-power mode is enabled by setting this bit to 1. the pga operates with reduced power consumption and reduced performance. the lpmode does not affect power or performance when the pga is not enabled. pgaen the pga enable bit controls the operation of the pga. a 1 enables and a 0 disables the pga. pga[2:0] the pga bits control the pga gain. the pga gain is set by: pga2 pga1 pga0 description 0 0 0 gain = 1 0 0 1 gain = 2 0 1 0 gain = 4 0 1 1 gain = 8 1 0 0 gain = 16 1 0 1 gain = 32 1 1 0 gain = 64 1 1 1 gain = 128 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 42 downloaded from: http:///
ctrl3: control register 3 (read/write) default = 0x1c bit name gpo_mode sync_mode calregsel nosysg nosyso noscg nosco default 0 0 1 1 1 0 0 this register is used to control the operation and calibration of the MAX11253. bit name description gpo_mode the value of this bit controls the gpo mode for sequencer mode 3. when set to 1, the gpo and the gpio pins are sequenced based on the channel mapping in the chmap1 and chmap0 registers. when set to 0, the gpo and gpio pins are directly controlled by the gpo_dir and gpio_ctrl registers, respectively, during conversion or standby state. this bit has no effect in sequencer modes 1 and 2. sync_mode this bit controls sync mode (see the conversion synchronization using sync pin and external clock section). when set to 1, the synchronization mode is enabled, when set to 0 it is disabled. calregsel this bit controls which calibration value is read during a calibration register inquiry. set this bit to 1 to read back the interface value. set this bit to 0 to read back the internal register value. nosysg the no system gain bit controls the use of the system gain calibration coeficient. set this bit to 1 to disable the use of the system gain value when computing the inal offset and gain corrected data value. set this bit to 0 to enable the use of the system gain value when computing the inal offset and gain corrected data value. nosyso the no system offset bit controls the use of the system offset calibration coeficient. set this bi t to 1 to disable the use of the system offset value when computing the inal offset and gain corrected data value. set this bit to 0 to enable the use of the system offset value when computing the inal offs et and gain corrected data value. noscg the no self-calibration gain bit controls the use of the self-calibration gain calibration coefici ent. set this bit to 1 to disable the use of the self-calibration gain value when computing the inal offset and gain corrected data value. set this bit to 0 to enable the use of the self-calibration gain value when computing the inal offset and gain corrected data value. nosco the no self-calibration offset bit controls the use of the self-calibration offset calibration coe ficient. set this bit to 1 to disable the use of the self-calibration offset value when computing the inal offset and gain corrected data value. set this bit to 0 to enable the use of the self-calibration offset value when computing the inal offset and gain corrected data value. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 43 downloaded from: http:///
gpio_ctrl: gpio control register (read/write) delay: delay register (read/write) default = 0x0000 bit name mux[7:0] gpo[7:0] default 0x00 0x00 bit name description mux[7:0] used to program the mux delay. the mux delay ranges from 4s to 1.02ms. the default value of 0x00 corresponds to no delay. 1 lsb = 4s of delay. gpo[7:0] used to program the gpo/gpio delay. the gpo/gpio delay ranges from 20s to 5.1ms. the default value of 0x00 corresponds to no delay. 1 lsb = 20s of delay. default = 0x4x bit name gpio1_en gpio0_en dir1 dir0 dio1 dio0 default 0 1 0 0 x x this register controls the direction and values of the general-purpose i/o (gpio) pins. bit name description gpio1_en this bit selects the functionality of the gpio1/sync pin. set this bit to 1 to use the pin as gpio, or set the bit to 0 to use the pin as sync input. gpio0_en this bit selects the functionality of the gpio0/clk pin. set this bit to 1 to use the pin as gpio, or set the bit to 0 to use the pin as external clock input. dir[1:0] the direction bits conigure the gpio pins either as input or output. dir1 corresponds to gpio1, while dir0 controls gpio0. set the dir bit to 1 to conigure the gpio pin as output. the output value of the gpio pin is determined by the value of the dio bit. set the dir bit to 0 to conigure the associated gpio pin as input. the logic input value of the gpio pin can be read back from the dio bit. dio[1:0] the data input/output bits relect the status of the gpio pins. dio1 corresponds to gpio1, while dio0 corresponds to gpio0. if the gpio pin is conigured as output, the pin is driven to the logic va lue of dio. if the gpio pin is conigured as input, dio relects the logic value seen at the pin. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 44 downloaded from: http:///
chmap1: channel map register (read/write) chmap0: channel map register (read/write) default = 0x00_0000 bit name ch5_gpo1 ch5_gpo0 ch5_ord2 ch5_ord1 ch5_ord0 ch5_en ch5_gpoen default 0 0 0 0 0 0 0 bit name ch4_gpo1 ch4_gpo0 ch4_ord2 ch4_ord1 ch4_ord0 ch4_en ch4_gpoen default 0 0 0 0 0 0 0 bit name ch3_gpo1 ch3_gpo0 ch3_ord2 ch3_ord1 ch3_ord0 ch3_en ch3_gpoen default 0 0 0 0 0 0 0 default = 0x00_0000 bit name ch2_gpo1 ch2_gpo0 ch2_ord2 ch2_ord1 ch2_ord0 ch2_en ch2_gpoen default 0 0 0 0 0 0 0 bit name ch1_gpo1 ch1_gpo0 ch1_ord2 ch1_ord1 ch1_ord0 ch1_en ch1_gpoen default 0 0 0 0 0 0 0 bit name ch0_gpo1 ch0_gpo0 ch0_ord2 ch0_ord1 ch0_ord0 ch0_en ch0_gpoen default 0 0 0 0 0 0 0 these registers are used to enable channels for scan, enable gpo/gpio pins for scan, program the channel scan order, and pair the gpo/gpio pins with its associated channel. these registers cannot be written during an active conversion. bit name description chx_gpo[1:0] used to map which gpo or gpio pin is activated when this channel is selected. the stat:gpoerr lag is set if more than one input channel is mapped to the same gpo/gpio pin. the decoding is as follows: chx_gpo1 chx_gpo0 description 0 0 gpo0 0 1 gpo1 1 0 gpio0 1 1 gpio1 chx_ord[2:0] deines the order during scan when the channel is enabled. the chx_ord[2:0] values of 000 and 111 are not allowed for the order of an enabled channel. the allowable orders are 001, 010, 011, 100, 101, 110 representing irst, second, third channel to be scanned, and so on. the value of 000 i s a default value and the value of 111 is greater than the number of scannable channels. a value greater than the number of enabled channels is invalid and will set an error condition at stat:orderr. setting a channels order to 000 or 111 and enabling it will set the stat:orderr lag in the stat registe r. if sequencer mode 3 is selected, and more channels are enabled for sequencing than available gpo/ gpio pins, then the sequence order of the channels for which a gpo/gpio pin is enabled must be lower than for the channels which do not have a gpo/gpio pin mapped to them. chx_en set this bit to 1 to enable scanning of this channel. set this bit to 0 to disable scanning of this channel. chx_gpoen used to enable activation of the gpo/gpio pins when this channel is selected during scan. set this bit to 1 to enable. set this bit to 0 to disable. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 45 downloaded from: http:///
seq: sequencer register (read/write) gpo_dir: gpo direct access register (read/write) default = 0x00 bit name mux2 mux1 mux0 mode1 mode0 gpodren mdren rdyben default 0 0 0 0 0 0 0 0 this register is used to control the operation of the sequencer when enabled. bit name description mux[2:0] binary channel selection for sequencer mode 1. valid channels are from 000 (channel 0) to 101 (channel 5). mode[1:0] sequencer mode is decoded as shown in the following table: mode1 mode0 description 0 0 sequencer mode 1 0 1 sequencer mode 2 1 0 sequencer mode 3 1 1 reserved. do not use. gpodren gpo/gpio delay enable. enables operation of the gpo/gpio switch delay. when enabled, the channel selection is delayed. the value of the delay is set by the delay:gpo bits. mdren mux delay enable. enables the timer setting in the delay:mux register to delay the conversion start of the selected channel. rdyben ready bar enable. when this bit is 1 the rdyb is inhibited from asserting in sequencer mode 2 and 3 until all channels are converted default = 0x00 bit name gpo1 gpo0 default 0 0 this register is used to turn on and off the general-purpose outputs directly after an associated bit is written except when ctrl3:gpo_ mode=1 during sequencer mode 3. when operating in sequencer mode 1 or 2, the activation of the gpos is immediate upon setting a bit to 1, and the deactivation of the gpos is immediate upon setting the bit to 0. in sleep state, the values in this register do not control the state of the gpos, as they all are deactivated. the register is writeable, but the values will not control the gpos in sleep mode. in standby state when ctrl3:gpo_mode=0, this register accepts writes and updates the state of the gpos immediately after the value of a bit changes. writes to this register are ignored when operating in mode 3 when ctrl3:gpo_mode=1. this register is enabled during system offset calibration, system gain calibration and self-calibration modes. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 46 downloaded from: http:///
soc: system offset calibration register (read/write) sgc: system gain calibration register (read/write) default = 0x00_0000 bit name b23 b22 b21 . b3 b2 b1 b0 default 0 0 0 . 0 0 0 0 the system offset calibration register is a 24-bit read/write register. the data written/read to/from this register is clocked in/out msb irst. this register holds the system offset calibration value. the format is in twos complement bin ary format. a system calibration does not overwrite the soc register. the readback value of this register depends on ctrl3:calregsel. a 1 reads back the user programmed value. a 0 reads back the results of an internal register as described in ctrl3:calregsel. the internal register can only be read during conversion. the system offset calibration value is subtracted from each conversion resultprovided the nosyso bit in the ctrl3 register is set to 0. the system offset calibration value is subtracted from the conversion result after self-calibration but before system gain correction. it is also applied prior to the 1x or 2x scale factor associated with bipolar and unipolar modes. when a system offset calibration is in progress, this register is not writable by the user. default = 0x7f_ffff bit name b23 b22 b21 . b3 b2 b1 b0 default 0 1 1 . 1 1 1 1 the system gain calibration register is a 24-bit read/write register. the data written/read to/from this register is clocked in/out msb irst. this register holds the system gain calibration value. the format is unsigned 24-bit binary. a system calibration does not overwrite the sgc register. the readback value of this register depends on ctrl3:calregsel. a 1 reads back the user programmed value. a 0 reads back the results of an internal register as described in ctrl3:calregsel. the internal register can only be read during conversion. the system gain calibration value is used to scale the offset corrected conversion resultprovided the nosysg bit in the ctrl3 register is set to 0. the system gain calibration value scales the offset corrected result by up to 2x or can correct a gain error of approximately -50%. the amount of positive gain error that can be corrected is determined by modulator overload characteristics, which may be as much as +25%. when a system gain calibration is in progress, this register is not writable by the user. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 47 downloaded from: http:///
scoc: self-calibration offset calibration register (read/write) scgc: self-calibration gain calibration register (read/write) default = 0x00_0000 bit name b23 b22 b21 . b3 b2 b1 b0 default 0 0 0 . 0 0 0 0 the self-calibration offset register is a 24-bit read/write register. the data written/read to/from this register is clocked in/out msb irst. this register holds the self-calibration offset value. the format is always in twos complemen t binary format. an internal self- calibration does not overwrite the scoc register. the readback value of this register depends on ctrl3:calregsel. a 1 reads back the user programmed value. a 0 reads back the results of an internal register as described in ctrl3:calregsel. the internal register can only be read during conversion. the self-calibration offset value is subtracted from each conversion resultprovided the nosco bit in the ctrl3 register is set to 0. the self-calibration offset value is subtracted from the conversion result before the self-calibration gain correction and before the system offset and gain correction. it is also applied prior to the 2x scale factor associated with unipolar mode. when a self-calibration is in progress, this register is not writable by the user. default = 0xbf_851b bit name b23 b22 b21 . b3 b2 b1 b0 default 1 0 1 . 1 0 1 1 the self-calibration gain register is a 24-bit read/write register. the data written/read to/from th is register is clocked in/out msb irst. this register holds the self-calibration gain value. the format is unsigned 24-bit binary. an internal self- calibration does not overwrite the scgc register. the readback value of this register depends on ctrl3:calregsel. a 1 reads back the user programmed value. a 0 reads back the results of an internal register as described in ctrl3:calregsel. the internal register can only be read during conversion. the self-calibration gain calibration value is used to scale the self-calibration offset corrected conversion result before the system offset and gain calibration values have been applied C provided the noscg bit in the ctrl3 register is set to 0. the self-calibration gain calibration value scales the self-calibration offset corrected conversion result by up to 2x or can correct a gain error of approximately C50%. the gain will be corrected to within 2 lsb. when a self- calibration is in progress, this register is not writable by the user. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 48 downloaded from: http:///
data[5:0]: data registers (read only) default = 0x0000 bit name d15 d14 d13 d3 d2 d1 d0 default 0 0 0 0 0 0 0 each data register holds the conversion result for the corresponding channel. data0 is the data register for channel 0, data1 is for channel 1, etc. each data register is a 16-bit read-only register. any attempt to write data to this location will have no effect. the data read from these registers is clocked out msb irst. the result is stored in a format according to the format bit in t he ctrl1 register. the data format while in unipolar mode is always offset binary. in offset binary format the most negative value is 0x0000, the midscale value is 0x8000 and the most positive value is 0xffff. in bipolar mode if the format bit = 1 then the data format is offset binary. if the format bit = 0, then the data format is twos complement. in twos complement the negative full-scale value is 0x8000, the midscale is 0x0000 and the positive full scale is 0x7fff. any input exceeding the available input range is limited to the minimum or maximum data value. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 49 downloaded from: http:///
+ denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. *ep = exposed pad. part temp range pin-package MAX11253atj+ -40c to +125c 32 tqfn-ep* MAX11253atj+t -40c to +125c 32 tqfn-ep* part package type package code outline no. land pattern no. MAX11253atj+ 32 tqfn t3255+4 21-0140 90-0012 MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface www.maximintegrated.com maxim integrated 50 chip information process: cmos ordering information package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. downloaded from: http:///
revision number revision date description pages changed 0 6/15 initial release maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX11253 16-bit, 6-channel, 64ksps, 6.2nv/hz pga, delta-sigma adc with spi interface ? 2015 maxim integrated products, inc. 51 revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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